From ea0961dfd2d2716d5ecc2fe535bcfeb413109831 Mon Sep 17 00:00:00 2001
From: Adam Ierymenko <adam.ierymenko@zerotier.com>
Date: Wed, 26 Feb 2020 11:32:54 -0800
Subject: [PATCH] docs

---
 node/MIMC52.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/node/MIMC52.cpp b/node/MIMC52.cpp
index e6cbbf678..29354866b 100644
--- a/node/MIMC52.cpp
+++ b/node/MIMC52.cpp
@@ -27,7 +27,7 @@ ZT_ALWAYS_INLINE uint64_t mulmod52(uint64_t a,uint64_t b,const uint64_t m) noexc
 {
 #if 0 // #ifdef ZT_ARCH_X64
 	// This works on X64 but is very slightly slower than the FPU trick on all tested cores. That's probably
-	// because FPU division is more heavily optimized in silicon than integer division.
+	// because FPU division is more heavily optimized in silicon than integer division on these chips.
 	uint64_t r;
 	__asm__ (
 		"mulq %2\n\t"