From 0413451a2ffbc7dddc607ce2bf64693b5e3880fd Mon Sep 17 00:00:00 2001
From: Duncaen <duncaen@voidlinux.org>
Date: Wed, 5 Oct 2022 15:21:57 +0200
Subject: [PATCH] u-boot-tools: update to 2022.10.

---
 .../fix-build-with-binutils-2.38.patch        | 42 +++++++++++++++++++
 srcpkgs/u-boot-tools/template                 |  4 +-
 2 files changed, 44 insertions(+), 2 deletions(-)
 create mode 100644 srcpkgs/u-boot-tools/patches/fix-build-with-binutils-2.38.patch

diff --git a/srcpkgs/u-boot-tools/patches/fix-build-with-binutils-2.38.patch b/srcpkgs/u-boot-tools/patches/fix-build-with-binutils-2.38.patch
new file mode 100644
index 00000000000..08e389f54c4
--- /dev/null
+++ b/srcpkgs/u-boot-tools/patches/fix-build-with-binutils-2.38.patch
@@ -0,0 +1,42 @@
+>From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+arch/riscv/cpu/mtrap.S: Assembler messages:
+arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
+arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
+arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
+arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
+
+Signed-off-by: Alexandre Ghiti <alexandre.ghiti at canonical.com>
+---
+ arch/riscv/Makefile | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0b80eb8d86..53d1194ffb 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ 	CMODEL = medany
+ endif
+ 
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
++ifeq ($(toolchain-need-zicsr-zifencei),y)
++	RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
++endif
++
++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
+ 	     -mcmodel=$(CMODEL)
+ 
+ PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)
+-- 
+2.32.0
+
diff --git a/srcpkgs/u-boot-tools/template b/srcpkgs/u-boot-tools/template
index 0ca8e34429c..77c53dc7858 100644
--- a/srcpkgs/u-boot-tools/template
+++ b/srcpkgs/u-boot-tools/template
@@ -1,6 +1,6 @@
 # Template file for 'u-boot-tools'
 pkgname=u-boot-tools
-version=2022.07
+version=2022.10
 revision=1
 wrksrc="u-boot-${version}"
 build_style=gnu-makefile
@@ -13,7 +13,7 @@ maintainer="Duncaen <duncaen@voidlinux.org>"
 license="GPL-2.0-or-later"
 homepage="https://www.denx.de/wiki/U-Boot/"
 distfiles="ftp://ftp.denx.de/pub/u-boot/u-boot-${version}.tar.bz2"
-checksum=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e
+checksum=50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8
 
 if [ "$CROSS_BUILD" ]; then
 	make_build_args+=" CROSS_BUILD_TOOLS=y CROSS_COMPILE=${XBPS_CROSS_TRIPLET}-"