diff --git a/srcpkgs/linux5.7/files/arm64-dotconfig b/srcpkgs/linux5.7/files/arm64-dotconfig index f71b2623e8e..bde04939d3d 100644 --- a/srcpkgs/linux5.7/files/arm64-dotconfig +++ b/srcpkgs/linux5.7/files/arm64-dotconfig @@ -6401,6 +6401,7 @@ CONFIG_DRM_AMD_ACP=y # Display Engine Configuration # CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_DCN=y # CONFIG_DRM_AMD_DC_HDCP is not set # CONFIG_DEBUG_KERNEL_DC is not set # end of Display Engine Configuration diff --git a/srcpkgs/linux5.7/patches/navi_alloc.patch b/srcpkgs/linux5.7/patches/navi_alloc.patch new file mode 100644 index 00000000000..02f794d63ec --- /dev/null +++ b/srcpkgs/linux5.7/patches/navi_alloc.patch @@ -0,0 +1,33 @@ +From 2fdd63feb95c6751526068c02f7512fd4bea6956 Mon Sep 17 00:00:00 2001 +From: Daniel Kolesa +Date: Sat, 8 Aug 2020 20:05:29 +0200 +Subject: [PATCH] dcn20_resource: use GFP_ATOMIC in validate_bandwidth_internal + +GFP_KERNEL may and will sleep, and this is being executed in +a non-preemptible context; this will mess things up since it's +called inbetween DC_FP_START/END, and rescheduling will result +in the DC_FP_END later being called in a different context (or +just crashing if any floating point/vector registers/instructions +are used after the call is resumed in a different context). + +Signed-off-by: Daniel Kolesa +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 2719cde..d37ede0 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -3031,7 +3031,7 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co + int vlevel = 0; + int pipe_split_from[MAX_PIPES]; + int pipe_cnt = 0; +- display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); ++ display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); + DC_LOGGER_INIT(dc->ctx->logger); + + BW_VAL_TRACE_COUNT(); +-- +2.28.0 + diff --git a/srcpkgs/linux5.7/patches/navi_arm64.patch b/srcpkgs/linux5.7/patches/navi_arm64.patch new file mode 100644 index 00000000000..7c7a39cc8f2 --- /dev/null +++ b/srcpkgs/linux5.7/patches/navi_arm64.patch @@ -0,0 +1,302 @@ +From eb493330aaa22cf7935c338f7d028bfeb1316b3b Mon Sep 17 00:00:00 2001 +From: Daniel Kolesa +Date: Sat, 8 Aug 2020 21:21:11 +0200 +Subject: [PATCH] drm/amd/display: add DCN support for Aarch64 + +This adds ARM64 support into the DCN. This mainly enables support +for Navi graphics cards. The dcn10 changes haven't been tested, +since I don't have the relevant hardware available, but there +is no way to conditionally disable them, so I've done them anyway. + +Signed-off-by: Daniel Kolesa +--- + drivers/gpu/drm/amd/display/Kconfig | 2 +- + drivers/gpu/drm/amd/display/dc/calcs/Makefile | 7 ++ + .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 7 ++ + drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 7 ++ + .../drm/amd/display/dc/dcn10/dcn10_resource.c | 81 ++++++++++++------- + drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 + + drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 + + drivers/gpu/drm/amd/display/dc/dml/Makefile | 13 +++ + drivers/gpu/drm/amd/display/dc/dsc/Makefile | 7 ++ + drivers/gpu/drm/amd/display/dc/os_types.h | 4 + + 10 files changed, 104 insertions(+), 32 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig +index 87858bc..21bf65b 100644 +--- a/drivers/gpu/drm/amd/display/Kconfig ++++ b/drivers/gpu/drm/amd/display/Kconfig +@@ -6,7 +6,7 @@ config DRM_AMD_DC + bool "AMD DC - Enable new display engine" + default y + select SND_HDA_COMPONENT if SND_HDA_CORE +- select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) ++ select DRM_AMD_DC_DCN if (X86 || PPC64 || (ARM64 && KERNEL_MODE_NEON)) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) + help + Choose this option if you want to use the new display engine + support for AMDGPU. This adds required support for Vega and +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile +index 4674aca..64f515d 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile +@@ -33,6 +33,10 @@ ifdef CONFIG_PPC64 + calcs_ccflags := -mhard-float -maltivec + endif + ++ifdef CONFIG_ARM64 ++calcs_rcflags := -mgeneral-regs-only ++endif ++ + ifdef CONFIG_CC_IS_GCC + ifeq ($(call cc-ifversion, -lt, 0701, y), y) + IS_OLD_GCC = 1 +@@ -53,6 +57,9 @@ endif + CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags) + CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags) + CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calc_math.o := $(calcs_rcflags) + + BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o + +diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +index c0f6a8c..3b74569 100644 +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +@@ -93,6 +93,13 @@ ifdef CONFIG_PPC64 + CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute) + endif + ++# prevent build errors: ++# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types ++# this file is unused on arm64, just like on ppc64 ++ifdef CONFIG_ARM64 ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := -mgeneral-regs-only ++endif ++ + AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21)) + + AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +index 62ad1a1..733e6e6 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +@@ -31,4 +31,11 @@ DCN10 = dcn10_init.o dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ + + AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10)) + ++# fix: ++# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types ++# aarch64 does not support soft-float, so use hard-float and handle this in code ++ifdef CONFIG_ARM64 ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn10/dcn10_resource.o := -mgeneral-regs-only ++endif ++ + AMD_DISPLAY_FILES += $(AMD_DAL_DCN10) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index ba849aa..924d967 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -1318,6 +1318,47 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx) + return value; + } + ++/* ++ * Some architectures don't support soft-float (e.g. aarch64), on those ++ * this function has to be called with hardfloat enabled, make sure not ++ * to inline it so whatever fp stuff is done stays inside ++ */ ++static noinline void dcn10_resource_construct_fp( ++ struct dc *dc) ++{ ++ if (dc->ctx->dce_version == DCN_VERSION_1_01) { ++ struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; ++ struct dcn_ip_params *dcn_ip = dc->dcn_ip; ++ struct display_mode_lib *dml = &dc->dml; ++ ++ dml->ip.max_num_dpp = 3; ++ /* TODO how to handle 23.84? */ ++ dcn_soc->dram_clock_change_latency = 23; ++ dcn_ip->max_num_dpp = 3; ++ } ++ if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { ++ dc->dcn_soc->urgent_latency = 3; ++ dc->debug.disable_dmcu = true; ++ dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; ++ } ++ ++ ++ dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; ++ ASSERT(dc->dcn_soc->number_of_channels < 3); ++ if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ ++ dc->dcn_soc->number_of_channels = 2; ++ ++ if (dc->dcn_soc->number_of_channels == 1) { ++ dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; ++ dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; ++ dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; ++ dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; ++ if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { ++ dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; ++ } ++ } ++} ++ + static bool dcn10_resource_construct( + uint8_t num_virtual_links, + struct dc *dc, +@@ -1435,37 +1476,15 @@ static bool dcn10_resource_construct( + memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); + memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); + +- if (dc->ctx->dce_version == DCN_VERSION_1_01) { +- struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; +- struct dcn_ip_params *dcn_ip = dc->dcn_ip; +- struct display_mode_lib *dml = &dc->dml; +- +- dml->ip.max_num_dpp = 3; +- /* TODO how to handle 23.84? */ +- dcn_soc->dram_clock_change_latency = 23; +- dcn_ip->max_num_dpp = 3; +- } +- if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { +- dc->dcn_soc->urgent_latency = 3; +- dc->debug.disable_dmcu = true; +- dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; +- } +- +- +- dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; +- ASSERT(dc->dcn_soc->number_of_channels < 3); +- if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ +- dc->dcn_soc->number_of_channels = 2; +- +- if (dc->dcn_soc->number_of_channels == 1) { +- dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; +- dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; +- dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; +- dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; +- if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { +- dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; +- } +- } ++#if defined(CONFIG_ARM64) ++ /* Aarch64 does not support -msoft-float/-mfloat-abi=soft */ ++ DC_FP_START(); ++ dcn10_resource_construct_fp(dc); ++ DC_FP_END(); ++#else ++ /* Other architectures we build for build this with soft-float */ ++ dcn10_resource_construct_fp(dc); ++#endif + + pool->base.pp_smu = dcn10_pp_smu_create(ctx); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile +index 5fcaf78..624cb13 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile +@@ -17,6 +17,10 @@ ifdef CONFIG_PPC64 + CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -maltivec + endif + ++ifdef CONFIG_ARM64 ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mgeneral-regs-only ++endif ++ + ifdef CONFIG_CC_IS_GCC + ifeq ($(call cc-ifversion, -lt, 0701, y), y) + IS_OLD_GCC = 1 +diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile +index 07684d3..51a2f3d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile +@@ -13,6 +13,10 @@ ifdef CONFIG_PPC64 + CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -maltivec + endif + ++ifdef CONFIG_ARM64 ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mgeneral-regs-only ++endif ++ + ifdef CONFIG_CC_IS_GCC + ifeq ($(call cc-ifversion, -lt, 0701, y), y) + IS_OLD_GCC = 1 +diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile +index e34c337..9845cf1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile +@@ -33,6 +33,10 @@ ifdef CONFIG_PPC64 + dml_ccflags := -mhard-float -maltivec + endif + ++ifdef CONFIG_ARM64 ++dml_rcflags := -mgeneral-regs-only ++endif ++ + ifdef CONFIG_CC_IS_GCC + ifeq ($(call cc-ifversion, -lt, 0701, y), y) + IS_OLD_GCC = 1 +@@ -60,9 +64,18 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags) + CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags) + CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) + CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags) + endif + CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags) + CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_rcflags) + + DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \ + +diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile b/drivers/gpu/drm/amd/display/dc/dsc/Makefile +index 3f66868..3c176c9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile +@@ -10,6 +10,10 @@ ifdef CONFIG_PPC64 + dsc_ccflags := -mhard-float -maltivec + endif + ++ifdef CONFIG_ARM64 ++dsc_rcflags := -mgeneral-regs-only ++endif ++ + ifdef CONFIG_CC_IS_GCC + ifeq ($(call cc-ifversion, -lt, 0701, y), y) + IS_OLD_GCC = 1 +@@ -30,6 +34,9 @@ endif + CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags) + CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags) + CFLAGS_$(AMDDALPATH)/dc/dsc/dc_dsc.o := $(dsc_ccflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_rcflags) ++CFLAGS_REMOVE_$(AMDDALPATH)/dc/dsc/dc_dsc.o := $(dsc_rcflags) + + DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o + +diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h +index 6d7bca5..6547a1a 100644 +--- a/drivers/gpu/drm/amd/display/dc/os_types.h ++++ b/drivers/gpu/drm/amd/display/dc/os_types.h +@@ -55,6 +55,10 @@ + #include + #define DC_FP_START() kernel_fpu_begin() + #define DC_FP_END() kernel_fpu_end() ++#elif defined(CONFIG_ARM64) ++#include ++#define DC_FP_START() kernel_neon_begin() ++#define DC_FP_END() kernel_neon_end() + #elif defined(CONFIG_PPC64) + #include + #include +-- +2.28.0 +