From f3a8913fc092f32c65deeea5ff63757de9a5178c Mon Sep 17 00:00:00 2001 From: Helmut Pozimski Date: Sun, 27 Oct 2019 08:17:34 +0100 Subject: [PATCH] dav1d: add patch to fix unaligned opcodes on aarch64 --- ...8f47f0eebcdfebb1753a786e3e1654b51ea4.patch | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 srcpkgs/dav1d/patches/a6228f47f0eebcdfebb1753a786e3e1654b51ea4.patch diff --git a/srcpkgs/dav1d/patches/a6228f47f0eebcdfebb1753a786e3e1654b51ea4.patch b/srcpkgs/dav1d/patches/a6228f47f0eebcdfebb1753a786e3e1654b51ea4.patch new file mode 100644 index 00000000000..e5fc394e638 --- /dev/null +++ b/srcpkgs/dav1d/patches/a6228f47f0eebcdfebb1753a786e3e1654b51ea4.patch @@ -0,0 +1,38 @@ +From a6228f47f0eebcdfebb1753a786e3e1654b51ea4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Martin=20Storsj=C3=B6?= +Date: Fri, 11 Oct 2019 13:17:36 +0300 +Subject: [PATCH] arm64: ipred: Make sure all symbols are aligned + +If building with debug information enabled, binutils error out with +"unaligned opcodes detected in executable segment", if there are +symbols (even local ones that don't end up in the symbol table) +that point to unaligned addresses in the text section. + +This fixes issue #300. +--- + src/arm/64/ipred.S | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/arm/64/ipred.S b/src/arm/64/ipred.S +index 41b3c1cb..9513212b 100644 +--- src/arm/64/ipred.S ++++ src/arm/64/ipred.S +@@ -2244,6 +2244,7 @@ L(ipred_cfl_ac_420_tbl): + .hword L(ipred_cfl_ac_420_tbl) - L(ipred_cfl_ac_420_w16) + .hword L(ipred_cfl_ac_420_tbl) - L(ipred_cfl_ac_420_w8) + .hword L(ipred_cfl_ac_420_tbl) - L(ipred_cfl_ac_420_w4) ++ .hword 0 + + L(ipred_cfl_ac_420_w16_tbl): + .hword L(ipred_cfl_ac_420_w16_tbl) - L(ipred_cfl_ac_420_w16_wpad0) +@@ -2432,6 +2433,7 @@ L(ipred_cfl_ac_422_tbl): + .hword L(ipred_cfl_ac_422_tbl) - L(ipred_cfl_ac_422_w16) + .hword L(ipred_cfl_ac_422_tbl) - L(ipred_cfl_ac_422_w8) + .hword L(ipred_cfl_ac_422_tbl) - L(ipred_cfl_ac_422_w4) ++ .hword 0 + + L(ipred_cfl_ac_422_w16_tbl): + .hword L(ipred_cfl_ac_422_w16_tbl) - L(ipred_cfl_ac_422_w16_wpad0) +-- +2.22.0 +